Click here to read more about T1.timing.
Each row in the table below represents one set of T1 libraries specific to a certain processor core and a certain compiler.
| Silicon/IP Vendor |
Core | Compiler | Availability (Variant ID) |
ISO26262 Version Available |
Controller Examples |
|---|---|---|---|---|---|
| Infineon | TC1.6.X, TC1.8 | TASKING VX-toolset | V3.5.x.x (57) | V3.4.0.1 | TC2xx, TC3xx, TC4x |
| Infineon | TC1.8 | TASKING SmartCode | V3.5.x.x (90) | V3.4.0.2 | TC4x |
| Infineon | TC1.6.X, TC1.8 | HighTec GCC | V3.5.x.x (15) | V3.4.0.1 | TC2xx, TC3xx, TC4x |
| Infineon | TC1.6.X, TC1.8 | HighTec TriCore LLVM | V3.5.x.x (91) | ✗ |
TC2xx, TC3xx, TC4x |
| Infineon | TC1.6.X | Wind River | V3.1.x.x (60) | ✗ |
TC2xx, TC3xx |
| Infineon | TC1.6.X, TC1.8 | Green Hills | V3.5.x.x (73) | ✗ |
TC2xx, TC3xx, TC4x |
| NXP/STM | e200z0-z4, z6, z7 | Green Hills | V3.5.x.x (54) / On Request (65/72) | ✗ |
MPC57xx, MPC56xx, MPC55xx, SPC58xx, SPC57xx, SPC56xx, etc. |
| NXP/STM | e200z2, z4, z7 | HighTec GCC | V3.5.x.x (44) | V3.4.0.0 | MPC57xx, MPC56xx, MPC55xx, SPC58xx, SPC57xx, SPC56xx, etc. |
| NXP/STM | e200z2, z4, z7 | Wind River | V3.5.x.x (56) | V3.4.0.0 | MPC57xx, MPC56xx, MPC55xx, SPC58xx, SPC57xx, SPC56xx, etc. |
| ARM | ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F | Texas Instruments | V2.5.8.0 (39) | ✗ |
TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc. |
| ARM | ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F | Green Hills | V3.5.x.x (78) | ✗ |
TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc. |
| ARM | ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F | HighTec GCC | V3.5.x.x (77) | V3.4.0.2 | TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc. |
| ARM | ARMv8-R: Cortex-R52 | HighTec CLANG | V3.5.x.x (87) | ✗ |
ST SR6 Stellar, NXP S32S |
| ARM | ARMv8-R: Cortex-R52 | Green Hills | V3.3.x.x (85) | V3.4.0.0 | ST SR6 Stellar, NXP S32S |
| ARM | ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * | GCC | V3.5.x.x (82) | ✗ |
Infineon Traveo II, LPC17xx, STM32F4xx, Atmel SAM V71, etc. |
| ARM | ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * | Green Hills | V3.5.x.x (83) | V3.4.0.0 | Infineon Traveo-II, LPC17xx, STM32F4xx, Atmel SAM V71, etc. |
| ARM | ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * | Keil (ARM Compiler for Embedded) | V3.5.x.x (84) | ✗ |
Infineon Traveo-II, LPC17xx, STM32F4xx, Atmel SAM V71, etc. |
| ARM | ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * | IAR | V3.5.x.x (69) | ✗ |
Infineon Traveo-II, LPC17xx, STM32F4xx, Atmel SAM V71, etc. |
| ARM | ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * | TASKING | V3.5.x.x (93) | ✗ |
Infineon Traveo-II, LPC17xx, STM32F4xx, Atmel SAM V71, etc. |
| Renesas | RH850 G3K/G3KH/G3M/G3MH/G4MH | Green Hills | V3.5.x.x (52) | V3.4.0.0 | RH850/C1x, RH850/F1x, RH850/P1x, RH850/E2x, etc. |
| Renesas | RH850 G3K/G3KH/G3M/G3MH/G4MH | Wind River | On Request (53) | ✗ |
RH850/C1x, RH850/F1x, RH850/P1x, RH850/E2x, etc. |
| Renesas | RH850 G3K/G3KH/G3M/G3MH/G4MH | Renesas | V3.5.x.x (92) | ✗ |
RH850/C1x, RH850/F1x, RH850/P1x, RH850/E2x, etc. |
| Texas Instruments | C66x | Texas Instruments | V3.5.x.x (89) | ✗ |
TMS320C66x, AWR2944, TDA3x |
(*) Cortex-M4 adds DSP and FPU to Cortex-M3. Cortex-M7 further adds a 64-bit bus and double precision FPU. T1 uses the shared sub-set of the instruction sets.
| Vendor | Operating System |
|---|---|
| Customer | Any in-house OS** |
| Customer | No OS - scheduling loop plus interrupts** |
| Elektrobit | EB tresos AutoCore OS |
| Elektrobit | EB tresos Safety OS |
| ETAS | RTA-OS |
| GLIWA | gliwOS |
| HighTec | PXROS-HR |
| Hyundai AutoEver | Mobilgene |
| KPIT Cummins | KPIT** |
| Mentor | VSTAR OS |
| Micriμm | μC/OS-II** |
| Vector | MICROSAR-OS |
| FreeRTOS** |
(**) T1 OS adaptation package T1-ADAPT-OS required.
(***) T1 OS adaptation package T1-ADAPT-OS required if 'OS Timing Hooks' are not supported.
| Target Interface | Comment |
|---|---|
| CAN | Low bandwidth requirement: typically one CAN message every 1 to 10ms. The bandwidth consumed by T1 is scalable and strictly deterministic. |
| CAN FD | Low bandwidth requirement: typically one CAN message every 1 to 10ms. The bandwidth consumed by T1 is scalable and strictly deterministic. |
| Diagnostic Interface | The diagnostic interface supports ISO14229 (UDS) as well as ISO14230, both via CAN with transportation protocol ISO15765-2 (addressing modes 'normal' and 'extended'). The T1-HOST-SW connects to the Diagnostic Interface using CAN. |
| Ethernet (IP:TCP, UDP) | TCP and UDP can be used, IP-address and port can be configured. |
| FlexRay | FlexRay is supported via the diagnostic interface and a CAN bridge. |
| JTAG/DAP | Interfaces exist to well-known debug environments such as Lauterbach TRACE32 and iSYSTEM winIDEA. The T1 JTAG interface requires an external debugger to be connected and, for data transfer, the target is halted. TriCore processors use DAP instead of JTAG. |
Click here to read more about T1.posix.
Each row in the table below represents one set of T1 libraries specific to a certain processor core and a certain compiler.
| Silicon/IP Vendor |
Core | Compiler | Availability (Variant ID) |
ISO26262 Version Available |
Controller Examples |
|---|---|---|---|---|---|
| ARM | ARMv8-A: Cortex-A5x, Cortex-A7x | GCC | V3.5.x.x (251/252/253) | ✗ |
NVIDIA Tegra, NXP S32G, TI TDAx, etc. |
| Intel | x86 64-bit | GCC | V3.5.x.x (254/255) | ✗ |
Intel Atom Denverton, etc. |
| Vendor | Operating System |
|---|---|
| Elektrobit | EB corbos Linux |
| BlackBerry | QNX 7.0/7.1 |
| Various Vendors | Embedded Linux (e.g. Yocto), Kernel >= 4.14 |
| Target Interface | Comment |
|---|---|
| Ethernet (IP:TCP, UDP) | TCP and UDP can be used, IP-address and port can be configured. |
Click here to read more about T1.accessPredictor.
| Silicon/IP Vendor |
Core | Controller Examples |
|---|---|---|
| Infineon | TC1.6.X, TC1.8 | TC2xx, TC3xx, TC4x |
| NXP/STM | e200z0-z4, z6, z7 | MPC57xx, MPC56xx, MPC55xx, SPC58xx, SPC57xx, SPC56xx, etc. |
Click here to read more about T1.stack.
| Silicon/IP Vendor |
Core | Controller Examples |
|---|---|---|
| Infineon | TC1.6.X, TC1.8 | TC2xx, TC3xx, TC4x |
| NXP/STM | e200z0-z4, z6, z7 | MPC57xx, MPC56xx, MPC55xx, SPC58xx, SPC57xx, SPC56xx, etc. |
| ARM | ARMv7-R: Cortex-R4, Cortex-R4F, Cortex-R5F | TMS570LS02x/03x/04x/05x/07x, TMS570LS11x/12x/21x/31x, TMS570LC43x, etc. |
| ARM | ARMv8-R: Cortex-R52 | ST SR6 Stellar, NXP S32S |
| ARM | ARMv7-M: Cortex-M3, Cortex-M4 *, Cortex-M7 * | Infineon Traveo II, LPC17xx, STM32F4xx, Atmel SAM V71, etc. |
| Renesas | RH850 G3K/G3KH/G3M/G3MH/G4MH | RH850/C1x, RH850/F1x, RH850/P1x, RH850/E2x, etc. |
| Intel | x86 64-bit | Intel Atom Denverton, etc. |
(*) Cortex-M4 adds DSP and FPU to Cortex-M3. Cortex-M7 further adds a 64-bit bus and double precision FPU. T1 uses the shared sub-set of the instruction sets.