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Resource optimization
As ever, resource optimization, especially of RAM, ROM and execution time but also of scheduling, has an important role in mass-production projects. It can reduce costs and increase reliability.

In many customer projects we demonstrated that, to some degree, something can be gained with little effort. The approach is very systematic. Initially, scheduling bottle-necks are inspected at the system level. Only at these places do code level optimizations offer a benefit. For example, optimising the idle task is unlikely to help. Apart from anything else, hot-spots can often be eased by modifying the scheduling and not the code.
When optimization at the code level is warranted, our detailed knowledge of common automotive processor architectures and widespread experience with optimizing compilers are invaluable.

Last but not least, we can deploy our timing suite T1, which is perfectly suited to guiding and measuring resource optimization.

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Embedded Testing 2019
Visit us at the Embedded Testing Conference in Munich (NH München Ost Conference Center), from 02nd - 04th of July!

NEW! T1 Timing suite V3.0 NEW!
Our Release V3.0 supports the features Streaming and POSIX. Click here for detailed information.

Interviews on YouTube
Check-out the interviews with GLIWA CEO Peter Gliwa on Matrickz TV. In this one Peter talks with MATRICKZ CEO Dr. Hasan Akram about timing in automotive software develeopment and in this one about entrepreneurship.

Interview

NEW Timing Poster
Our new poster explains automotive timing by contrasting AUTOSAR CP and AUTOSAR AP and even going one step further. For AUTOSAR AP it includes suggestions of how the usual timing parameters may be mapped.
Click here for downloading the PDF version or let us know if you would like to receive your own DIN-A1 hard-copy.

Neues Timingposter klein

NEW product T1.accessPredictor
Upset by MPU exceptions in the field? T1.accessPredictor allows you to check for any memory access violations before even flashing the software. It will perform a static analysis by disassembling the binary, building up the call-tree and identifying r/w memory accesses for each function. No source code required!

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T1 supports TC39x
Synchronized traces from 6 cores!
T1 makes it happen. Click here, to view a screenshot of T1 with 6 synchronized traces and some cross-core communications.

AURIX TC399

More details on the AURIX 2G can be found in Infineon's official press-release.
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